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FEATURES

LTC6240/LTC6241/LTC6242 Single/Dual/Quad 18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amps DESCRIPTIO
The LTC(R)6240/6241/LTC6242 are single, dual and quad low noise, low offset, rail-to-rail output, unity gain stable CMOS op amps that feature 1pA of input bias current. Input bias current is guaranteed to be 1pA max on the single LTC6240. The 0.1Hz to 10Hz noise of only 550nVP-P, along with an offset of just 125V are significant improvements over traditional CMOS op amps. Additionally, noise is guaranteed to be less than 10nV/Hz at 1kHz. An 18MHz gain bandwidth, and 10V/s slew rate, along with the wide supply range and low input capacitance, make them perfect for use as fast signal processing amplifiers. These op amps have an output stage that swings within 30mV of either supply rail to maximize the signal dynamic range in low supply applications. The input common mode range extends to the negative supply. They are fully specified on 3V and 5V, and an HV version guarantees operation on supplies up to 5V. The LTC6240 is available in the 8-pin SO and the 5-pin SOT-23 packages. The LTC6241 is available in the 8-pin SO, and for compact designs it is packaged in a tiny dual fine pitch leadless (DFN) package. The LTC6242 is available in the 16-Pin SSOP as well as the 5mm x 3mm DFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

0.1Hz to 10Hz Noise: 550nVP-P Input Bias Current: 0.2pA (Typ at 25C) 1pA Max (LT6240) Low Offset Voltage: 125V Max Low Offset Drift: 2.5V/C Max Gain Bandwidth Product: 18MHz Output Swings Rail-to-Rail Supply Operation: 2.8V to 6V LTC6240/LTC6241/LTC6242 2.8V to 5.5V LTC6240HV/LTC6241HV/LTC6242HV Low Input Capacitance H Grade Temperature Range: -40C to 125C Single LTC6240 in 5-Pin SOT-23 Package and 8-Pin SO for PCB Guard Ring Dual LTC6241 in 8-Pin SO and Tiny DFN Packages Quad LTC6242 in 16-Pin SSOP and 5mm x 3mm DFN Packages
APPLICATIO S

Photo Diode Amplifiers Charge Coupled Amplifiers Low Noise Signal Processing Medical Instrumentation High Impedance Transducer Amplifier
TYPICAL APPLICATIO
C4 10pF R1 200k VIN C1 10pF
Low Noise Single-Ended Input to Differential Output Amplifier
C3 10pF NOISE VOLTAGE (nV/Hz) R4 4.99k R3 4.99k +2.5V 60 50 40 30 20 10 VOUT- 0
Noise Voltage vs Frequency
TA = 25C VS = 2.5V VCM = 0V
-
1/2 LTC6241 VOUT+
-
1/2 LTC6241
+
-2.5V R2 200k
+
C2 10pF
1
6241 TA01a
U
10
U
U
100 1k FREQUENCY (Hz)
10k
100k
6241 TA01b
624012fc
1
LTC6240/LTC6241/LTC6242 ABSOLUTE AXI U RATI GS
Total Supply Voltage (V+ to V-) LTC6240/LTC6241/LTC6242 ...................................7V LTC6240HV/LTC6241HV/LTC6242HV ...................12V Input Voltage.......................... (V+ + 0.3V) to (V- - 0.3V) Input Current........................................................10mA Output Short Circuit Duration (Note 2) ............ Indefinite Operating Temperature Range LTC6240C/LTC6241C/LTC6242C.......... -40C to 85C LTC6240I/LTC6241I/LTC6242I ............. -40C to 85C LTC6240H/LTC6241H/LTC6242H ....... -40C to 125C
PACKAGE/ORDER I FOR ATIO
TOP VIEW TOP VIEW -IN 2 +IN 3 V- 4 - OUT 1 V- 2 + - +IN 3 4 -IN 5 V+ NC 1 8 7 6 5 NC V+ OUT NC
S5 PACKAGE 5-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 250C/W
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 190C/W
TOP VIEW TOP VIEW OUT A 1 -IN A 2 +IN A 3 V
-
8 V+ A B 7 OUT B 6 -IN B 5 +IN B
OUT A 1 -IN A 2 +IN A 3 V- 4 A B
4
DD PACKAGE 8-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W UNDERSIDE METAL CONNECTED TO V- (PCB CONNECTION OPTIONAL)
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 190C/W
2
U
+
U
W
WW U
W
(Note 1)
Specified Temperature Range (Note 3) LTC6240C/LTC6241C/LTC6242C.............. 0C to 70C LTC6240I/LTC6241I/LTC6242I ............. -40C to 85C LTC6240H/LTC6241H/LTC6242H ....... -40C to 125C Junction Temperature ........................................... 150C DHC, DD Package ............................................. 125C Storage Temperature Range....................-65C to 150C DHC, DD Package ...............................-65C to 125C Lead Temperature (Soldering, 10 sec) .................. 300C
ORDER PART NUMBER S5 PART MARKING* LTC6240CS5 LTC6240HVCS5 LTC6240IS5 LTC6240HVIS5 LTC6240HS5 LTC6240HVHS5 ORDER PART NUMBER LTC6240CS8 LTC6240HVCS8 LTC6240IS8 LTC6240HVIS8 LTC6240HS8 LTC6240HVHS8 LTC6241CDD LTC6241HVCDD LTC6241IDD LTC6241HVIDD ORDER PART NUMBER LTC6241CS8 LTC6241HVCS8 LTC6241IS8 LTC6241HVIS8 LTC6241HS8 LTC6241HVHS8 LTCRR LTCRS LTCRR LTCRS LTCRR LTCRS S8 PART MARKING 6240 6240HV 6240I 240HVI 6240H 240HVH LBPD LBRR LBPD LBRR S8 PART MARKING 6241 6241HV 6241I 241HVI 6241H 241HVH
624012fc
ORDER PART NUMBER DD PART MARKING*
8 7 6 5
V+ OUT B -IN B +IN B
LTC6240/LTC6241/LTC6242 PACKAGE/ORDER I FOR ATIO
TOP VIEW TOP VIEW OUT A -IN A +IN A V
+
1 2 3 4 5 6 7 8 B 17 C A D
16 OUT D 15 -IN D 14 +IN D 13 V
-
OUT A -IN A +IN A V+ +IN B -IN B OUT B NC
1 2 3 4 5 6 7 8 B C A D
+IN B -IN B OUT B NC
12 +IN C 11 -IN C 10 OUT C 9 NC
DHC16 PACKAGE 16-LEAD (5mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W UNDERSIDE METAL CONNECTED TO V- (PCB CONNECTION OPTIONAL)
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150C, JA = 135C/W
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
AVAILABLE OPTIO S
PART NUMBER LTC6240CS5 LTC6240CS8 LTC6240HVCS5 LTC6240HVCS8 LTC6240IS5 LTC6240IS8 LTC6240HVIS5 LTC6240HVIS8 LTC6240HS5 LTC6240HS8 LTC6240HVHS5 LTC6240HVHS8 LTC6241CS8 LTC6241CDD LTC6241HVCS8 LTC6241HVCDD LTC6241IS8 LTC6241IDD LTC6241HVIS8 LTC6241HVIDD LTC6241HS8 LTC6241HVHS8 AMPS/PACKAGE 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 SPECIFIED TEMP RANGE 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 125C -40C to 125C -40C to 125C -40C to 125C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 125C -40C to 125C SPECIFIED SUPPLY VOLTAGE 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V, 5V PACKAGE SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SO-8 DD SO-8 DD SO-8 DD SO-8 DD SO-8 SO-8 PART MARKING LTCRR 6240 LTCRS 6240HV LTCRR 6240I LTCRS 240HVI LTCRR 6240H LTCRS 240HVH 6241 LBPD 6241HV LBRR 6241I LBPD 241HVI LBRR 6241H 241HVH
624012fc
U
ORDER PART NUMBER DHC PART MARKING*
16 OUT D 15 -IN D 14 +IN D 13 V - 12 +IN C 11 -IN C 10 OUT C 9 NC
W
U
LTC6242CDHC LTC6242HVCDHC LTC6242IDHC LTC6242HVIDHC ORDER PART NUMBER LTC6242CGN LTC6242HVCGN LTC6242IGN LTC6242HVIGN LTC6242HGN LTC6242HVHGN
6242 6242HV 6242 6242HV GN PART MARKING 6242 6242HV 6242I 242HVI 6242H 242HVH
U
3
LTC6240/LTC6241/LTC6242 AVAILABLE OPTIO S
PART NUMBER LTC6242CGN LTC6242CDHC LTC6242HVCGN LTC6242HVCDHC LTC6242IGN LTC6242IDHC LTC6242HVIGN LTC6242HVIDHC LTC6242HGN LTC6242HVHGN AMPS/PACKAGE 4 4 4 4 4 4 4 4 4 4 SPECIFIED TEMP RANGE 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 125C -40C to 125C SPECIFIED SUPPLY VOLTAGE 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V, 5V PACKAGE GN DHC GN DHC GN DHC GN DHC GN GN PART MARKING 6242 6242 6242HV 6242HV 6242I 6242 242HVI 6242HV 6242H 242HVH
ELECTRICAL CHARACTERISTICS
SYMBOL VOS PARAMETER Input Offset Voltage (Note 4)
(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
CONDITIONS LTC6241 S8 0C to 70C -40C to 85C LTC6242 GN 0C to 70C -40C to 85C LTC6240 0C to 70C -40C to 85C LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C VOS Match Channel-to-Channel (Note 5) LTC6241 S8 0C to 70C -40C to 85C LTC6242 GN 0C to 70C -40C to 85C LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C TC VOS IB Input Offset Voltage Drift (Note 6) Input Bias Current (Notes 4, 7) LTC6241, LTC6242

IOS
Input Offset Current (Notes 4, 7)
Input Noise Voltage
4
U
MIN
TYP 40
MAX 125 250 300 150 275 300 175 300 350 550 650 725 160 300 375 185 325 400 650 700 750 2.5 75
UNITS V V V V V V V V V V V V V V V V V V V V V V/C pA pA pA pA pA pA pA pA nVP-P
624012fc
50

50

100

40

50

150

0.7 0.2 0.2
LTC6240
1 75 75
LTC6241, LTC6242
0.2 0.2
LTC6240 0.1Hz to 10Hz
1 75
550
LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS
SYMBOL en in RIN CIN PARAMETER Input Noise Voltage Density Input Noise Current Density (Note 8) Input Resistance Input Capacitance Differential Mode Common Mode Input Voltage Range Common Mode Rejection CMRR Match Channel-to-Channel (Note 5) AVOL Large Signal Voltage Gain VO = 1V to 4V RL = 10k to VS/2 0C to 70C -40C to 85C VO = 1.5V to 3.5V RL = 1k to VS/2 0C to 70C -40C to 85C VOL Output Voltage Swing Low (Note 9) No Load ISINK = 1mA ISINK = 5mA No Load ISOURCE = 1mA ISOURCE = 5mA VS = 2.8V to 6V, VCM = 0.2V Common Mode f = 100kHz 3.5 3 Guaranteed by CMRR 0V VCM 3.5V

(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
CONDITIONS f = 1kHz MIN TYP 7 0.56 1012 MAX 10 UNITS nV/Hz fA/Hz pF pF 3.5 105 95 1600 V dB dB V/mV V/mV V/mV V/mV V/mV V/mV 30 75 325 30 75 325 mV mV mV mV mV mV dB dB V 30 1.8

VCM CMRR
0 80 76 425 300 200 90 60 50

215

7 40 190 11 45 190 80 74 2.8 15 104 100
VOH
Output Voltage Swing High (Note 9)
PSRR
Power Supply Rejection PSRR Match Channel-to-Channel (Note 5) Minimum Supply Voltage (Note 10)
ISC IS
Short-Circuit Current Supply Current per Amplifier LTC6241, LTC6242 0C to 70C -40C to 85C LTC6240 0C to 70C -40C to 85C
mA 2.2 2.3 2.4 2.4 2.5 2.6 mA mA mA mA mA mA MHz V/s MHz ns
2

GBW SR FPBW ts
Gain Bandwidth Product Slew Rate (Note 11) Full Power Bandwidth (Note 12) Settling Time
Frequency = 20kHz, RL = 1k AV = -2, RL = 1k VOUT = 3VP-P, RL = 1k VSTEP = 2V, AV = -1, RL = 1k, 0.1%
13 5 0.53
18 10 1.06 1100
624012fc
5
LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS
SYMBOL VOS PARAMETER Input Offset Voltage (Note 4)
(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
CONDITIONS LTC6241 S8 0C to 70C -40C to 85C LTC6242 GN 0C to 70C -40C to 85C LTC6240 0C to 70C -40C to 85C LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C VOS Match Channel-to-Channel (Note 5) LTC6241 S8 0C to 70C -40C to 85C LTC6242 GN 0C to 70C -40C to 85C LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C Input Offset Voltage Drift (Note 6) Input Bias Current (Notes 4, 7) LTC6241, LTC6242 LTC6240
MIN

TYP 40
60

50

100

40

60

150

TC VOS IB
0.7 0.2 0.2 0.2
MAX 175 275 325 200 275 325 200 325 375 550 650 725 200 325 400 225 325 400 650 700 750 2.5 75 1 75 75 1 75 1.5
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
LTC6240
0.2

VCM CMRR
AVOL
Input Voltage Range Common Mode Rejection CMRR Match Channel-to-Channel (Note 5) Large Signal Voltage Gain
Guaranteed by CMRR 0V VCM 1.5V
0 78 76 140 100 75
100 95 600
UNITS V V V V V V V V V V V V V V V V V V V V V V/C pA pA pA pA pA pA pA pA V dB dB V/mV V/mV V/mV mV mV mV mV dB dB V mA mA mA mA mA mA mA MHz
624012fc
VOL VOH PSRR
Output Voltage Swing Low (Note 9) Output Voltage Swing High (Note 9) Power Supply Rejection PSRR Match Channel-to-Channel (Note 5) Minimum Supply Voltage (Note 10) Short-Circuit Current Supply Current per Amplifier
VO = 1V to 2V RL = 10k to VS/2 0C to 70C -40C to 85C No Load ISINK = 1mA No Load ISOURCE = 1mA VS = 2.8V to 6V, VCM = 0.2V

80 74 2.8 3
3 65 4 70 104 100 6 1.4
30 110 30 120
ISC IS
GBW
Gain Bandwidth Product
LTC6241, LTC6242 0C to 70C -40C to 85C LTC6240 0C to 70C -40C to 85C Frequency = 20kHz, RL = 1k

1.5

1.7 1.8 1.9 1.9 2 2.1
12
17
6
LTC6240/LTC6241/LTC6242
(LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 0V unless otherwise noted.
SYMBOL VOS CONDITIONS LTC6241 S8 0C to 70C -40C to 85C LTC6242 GN 0C to 70C -40C to 85C LTC6240 0C to 70C -40C to 85C LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C VOS Match Channel-to-Channel (Note 5) LTC6241 S8 0C to 70C -40C to 85C LTC6242 GN 0C to 70C -40C to 85C LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C Input Offset Voltage Drift (Note 6) Input Bias Current (Notes 4, 7) LTC6241, LTC6242 LTC6240
ELECTRICAL CHARACTERISTICS
PARAMETER Input Offset Voltage (Note 4)
MIN

TYP 50
60

60

100

50

60

150

TC VOS IB
0.7 0.5 0.5 0.2
MAX 175 275 325 200 275 325 250 350 400 550 650 725 200 325 400 225 325 400 650 700 750 2.5 75 1 75 75 1 75 10
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
LTC6240
0.2 550 7 0.56 1012 3.5 3
en in RIN CIN VCM CMRR
Input Noise Voltage Input Noise Voltage Density Input Noise Current Density (Note 8) Input Resistance Input Capacitance Differential Mode Common Mode Input Voltage Range Common Mode Rejection CMRR Match Channel-to-Channel (Note 5) Large Signal Voltage Gain
0.1Hz to 10Hz f = 1kHz Common Mode f = 100kHz
UNITS V V V V V V V V V V V V V V V V V V V V V V/C pA pA pA pA pA pA pA pA nVP-P nV/Hz fA/Hz pF pF V dB dB V/mV V/mV V/mV V/mV V/mV V/mV mV mV mV
Guaranteed by CMRR -5V VCM 3.5V

-5 83 76 775 600 500 150 90 75
3.5 105 95 2700
AVOL
VOL
Output Voltage Swing Low (Note 9)
VO = -3.5V to 3.5V RL = 10k 0C to 70C -40C to 85C RL = 1k 0C to 70C -40C to 85C No Load ISINK = 1mA ISINK = 10mA

360
15 45 360
30 75 550
624012fc
7
LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS
SYMBOL VOH PSRR PARAMETER Output Voltage Swing High (Note 9)
(LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 0V unless otherwise noted.
CONDITIONS No Load ISOURCE = 1mA ISOURCE = 10mA VS = 2.8V to 11V, VCM = 0.2V MIN

ISC IS
Power Supply Rejection PSRR Match Channel-to-Channel (Note 5) Minimum Supply Voltage (Note 10) Short-Circuit Current Supply Current per Amplifier
85 82 2.8 15
TYP 15 45 360 110 106 35 2.5
MAX 30 75 550
UNITS mV mV mV dB dB V mA mA mA mA mA mA mA MHz V/s MHz ns
GBW SR FPBW ts
Gain Bandwidth Product Slew Rate (Note 11) Full Power Bandwidth (Note 12) Settling Time
LTC6241, LTC6242 0C to 70C -40C to 85C LTC6240 0C to 70C -40C to 85C Frequency = 20kHz, RL = 1k AV = -2, RL = 1k VOUT = 3VP-P, RL = 1k VSTEP = 2V, AV = -1, RL = 1k, 0.1%

2.7

3.2 3.3 3.7 3.3 3.4 3.8
13 5.5 0.58
18 10 1.06 900
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL VOS PARAMETER Input Offset Voltage (Note 4) CONDITIONS LTC6241 S8
MIN
TYP 40 50
MAX 125 400 150 400 175 450 160 400 185 400 2.5 1.5 1 2.5 150 1 750 3.5
UNITS V V V V V V V V V V V/C pA nA pA nA pA pA pA pA V dB dB
LTC6242 GN
LTC6240
50 40
VOS Match Channel-to-Channel (Note 5) LTC6241 S8 LTC6242 GN
50

TC VOS IB
Input Offset Voltage Drift (Note 6) Input Bias Current (Notes 4, 7)
LTC6241, LTC6242
0.7 0.2 0.2
LTC6240
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
0.2 0.2

LTC6240 VCM CMRR Input Voltage Range Common Mode Rejection CMRR Match Channel-to-Channel (Note 5) Large Signal Voltage Gain Guaranteed by CMRR 0V VCM 3.5V 0 78 74 425 200 90 40
AVOL
VO = 1V to 4V RL = 10k to VS/2 VO = 1.5V to 3.5V RL = 1k to VS/2
1600
V/mV V/mV V/mV V/mV
624012fc
215
8
LTC6240/LTC6241/LTC6242
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL VOL PARAMETER Output Voltage Swing Low (Note 9) CONDITIONS No Load ISINK = 1mA ISINK = 5mA No Load ISOURCE = 1mA ISOURCE = 5mA VS = 2.8V to 6V, VCM = 0.2V

ELECTRICAL CHARACTERISTICS
MIN
TYP
MAX 30 85 325 30 85 325
UNITS mV mV mV mV mV mV dB dB V mA mA mA mA mA MHz V/s MHz
VOH
Output Voltage Swing High (Note 9)
PSRR
ISC IS
Power Supply Rejection PSRR Match Channel-to-Channel (Note 5) Minimum Supply Voltage (Note 10) Short-Circuit Current Supply Current per Amplifier
78 74 2.8 15 1.8 2.2 2.4 2.4 2.8
LTC6241, LTC6242
LTC6240
2

GBW SR FPBW
Gain Bandwidth Product Slew Rate (Note 11) Full Power Bandwidth (Note 12)
Frequency = 20kHz, RL = 1k AV = -2, RL = 1k VOUT = 3VP-P, RL = 1k
12 4.5 0.48
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL VOS PARAMETER Input Offset Voltage (Note 4) CONDITIONS LTC6241 S8
MIN
TYP 40 60
MAX 175 400 200 400 200 450 200 400 225 400 2.5 1.5
UNITS V V V V V V V V V V V/C pA nA pA nA pA pA pA pA V dB dB
LTC6242 GN
LTC6240
50 40
VOS Match Channel-to-Channel (Note 5) LTC6241 S8 LTC6242 GN
60

TC VOS IB
Input Offset Voltage Drift (Note 6) Input Bias Current (Notes 4, 7) LTC6241, LTC6242
0.7 0.2
LTC6240
0.2 0.2
1 2.5 150
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242 LTC6240
0.2

1 750 1.5
VCM CMRR
Input Voltage Range Common Mode Rejection CMRR Match Channel-to-Channel (Note 5)
Guaranteed by CMRR 0V VCM 1.5V
0 75 74 140 65 600
AVOL
Large Signal Voltage Gain
VO = 1V to 2V RL = 10k to VS/2
V/mV V/mV
624012fc
9
LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS
SYMBOL VOL VOH PSRR PARAMETER Output Voltage Swing Low (Note 9) Output Voltage Swing High (Note 9) Power Supply Rejection PSRR Match Channel-to-Channel (Note 5) Minimum Supply Voltage (Note 10) ISC IS Short-Circuit Current Supply Current per Amplifier LTC6241, LTC6242
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
CONDITIONS No Load ISINK = 1mA No Load ISOURCE = 1mA VS = 2.8V to 6V, VCM = 0.2V

MIN
TYP
MAX 30 130 30 130
UNITS mV mV mV mV dB dB V mA
78 74 2.8 2.5 1.4 1.5 1.7 1.9 1.9 2.1
mA mA mA mA MHz
LTC6240
GBW
Gain Bandwidth Product
Frequency = 20kHz, RL = 1k
10
(LTC6240HVH/LTC6241HVH/LTC6242HVH) The denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, VCM = 0V unless otherwise noted.
SYMBOL VOS PARAMETER Input Offset Voltage (Note 4) CONDITIONS LTC6241 S8
MIN
TYP 50 60
MAX 175 400 200 400 250 450 200 400 225 400 2.5 1.5
UNITS V V V V V V V V V V V/C pA nA pA nA pA pA pA pA V dB dB
LTC6242 GN
LTC6240
60 50
VOS Match Channel-to-Channel (Note 5) LTC6241 S8 LTC6242 GN
60

TC VOS IB
Input Offset Voltage Drift (Note 6) Input Bias Current (Notes 4, 7) LTC6241, LTC6242
0.7 0.5
LTC6240
0.5 0.2
1 2.5 150
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242 LTC6240
0.2

1 750 3.5
VCM CMRR
Input Voltage Range Common Mode Rejection CMRR Match Channel-to-Channel (Note 5)
Guaranteed by CMRR -5V VCM 3.5V
-5 80 76 775 350 150 60 2700 360
AVOL
Large Signal Voltage Gain
VO = -3.5V to 3.5V RL = 10k RL = 1k

V/mV V/mV V/mV V/mV
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10
LTC6240/LTC6241/LTC6242
(LTC6240HVH/LTC6241HVH/LTC6242HVH) The denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, VCM = 0V unless otherwise noted.
SYMBOL VOL PARAMETER Output Voltage Swing Low (Note 9) CONDITIONS No Load ISINK = 1mA ISINK = 10mA No Load ISOURCE = 1mA ISOURCE = 10mA VS = 2.8V to 11V, VCM = 0.2V

ELECTRICAL CHARACTERISTICS
MIN
TYP
MAX 30 85 600 30 85 600
UNITS mV mV mV mV mV mV dB dB V mA
VOH
Output Voltage Swing High (Note 9)
PSRR
Power Supply Rejection PSRR Match Channel-to-Channel (Note 5) Minimum Supply Voltage (Note 10)
83 82 2.8 15 2.5 3.2 3.7 3.3 3.8
ISC IS
Short-Circuit Current Supply Current per Amplifier LTC6241, LTC6242
mA mA mA mA MHz V/s MHz
LTC6240
2.7

GBW SR FPBW
Gain Bandwidth Product Slew Rate (Note 11) Full Power Bandwidth (Note 12)
Frequency = 20kHz, RL = 1k AV = -2, RL = 1k VOUT = 3VP-P, RL = 1k
12 5 0.53
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 3: The LTC6240C/LTC6240HVC/LTC6241C/LTC6241HVC, LTC6242C/ LTC6242HVC are guaranteed to meet specified performance from 0C to 70C. They are designed, characterized and expected to meet specified performance from -40C to 85C, but are not tested or QA sampled at these temperatures. The LTC6240I/LTC6240HVI, LTC6241I/LTC6241HVI, LTC6242I/LTC6242HVI are guaranteed to meet specified performance from -40C to 85C. All versions of the LTC6240H/LTC6241H/LTC6242H are guaranteed to meet specified performance from -40C to 125C. Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection devices are used extensively internal to the LTC6240/LTC6241/LTC6242; however, high electrostatic discharge can damage or degrade the device. Use proper ESD handling precautions. Note 5: Matching parameters are the difference between the two amplifiers A and D and between B and C of the LTC6242; between the two amplifiers of the LTC6241. CMRR and PSRR match are defined as follows: CMRR
and PSRR are measured in V/V on the matched amplifiers. The difference is calculated between the matching sides in V/V. The result is converted to dB. Note 6: This parameter is not 100% tested. Note 7: Bias current at TA = 25C is 100% tested and guaranteed for the LTC6240 in the S8 package. The LTC6240S5, LTC6241 and LTC6242 are expected to achieve the same performance as the LTC6240S8. All parts are guaranteed to meet specifications over temperature. Note 8: Current noise is calculated from the formula: in = (2qIB)1/2 where q = 1.6 x 10-19 coulomb. The noise of source resistors up to 50G dominates the contribution of current noise. See also Typical Characteristics curve Noise Current vs Frequency. Note 9: Output voltage swings are measured between the output and power supply rails. Note 10: Minimum supply voltage is guaranteed by the power supply rejection ratio test. Note 11: Slew rate is measured in a gain of -2 with RF = 1k and RG = 500. On the LTC6240/LTC6241/LTC6242, VS = 2.5V, VIN is 1V and VOUT slew rate is measured between -1V and +1V. On the LTC6240HV/ LTC6241HV/LTC6242HV, VIN is 2V and VOUT slew rate is measured between -2V and +2V. Note 12: Full-power bandwidth is calculated from the slew rate: FPBW = SR/VP-P.
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11
LTC6240/LTC6241/LTC6242 TYPICAL PERFOR A CE CHARACTERISTICS
VOS Distribution LTC6241
90 VS = 2.5V 80 SO-8 PACKAGE 70 NUMBER OF UNITS NUMBER OF UNITS 60 50 40 30 20 20 10 0 -70 -50 -30 -10 10 30 50 INPUT OFFSET VOLTAGE (V) 70
6241 G01
80 60 40
NUMBER OF UNITS
VOS Distribution LTC6240
35 30 PERCENT OF UNITS NUMBER OF UNITS 25 20 15 10 5 0 -110 -90 -70 -50 -30 -10 10 30 50 INPUT OFFSET VOLTAGE (V) VS = 2.5V 18 16 14 12 10 8 6 4 2 70
SUPPLY CURRENT PER AMP (mA)
Offset Voltage vs Input Common Mode Voltage
300 250 200 OFFSET VOLTAGE (V) 150 100 50 0 -50 -100 -150 -200 -250 -300 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 INPUT COMMON MODE VOLTAGE (V)
6241 G05
INPUT BIAS CURRENT (pA)
100
INPUT BIAS CURRENT (pA)
TA = 125C
TA = 25C TA = -55C
12
UW
6241 G43
VOS Distribution LTC6241
120 100 VS = 2.5V DD PACKAGE 16 14 12 10 8 6 4 2 -350 -250 -150 -50 50 150 250 INPUT OFFSET VOLTAGE (V) 350
6241 G02
VOS Temperature Coefficient Distribution LTC6241
VS = 2.5V 2 LOTS -55C TO 125C
0
0 -1.0 -0.6 -0.2 0.2 0.6 1.0 DISTRIBUTION (V/C) 1.4 1.8
6241 G03
VOS Temperature Coefficient Distribution LTC6240
VS = 5V, 0 VCM = 2.5V 2 LOTS -40C TO 125C SO-8 AND SOT23 PACKAGES 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.2 0.2 0.6 1.0 1.4 DISTRIBUTION (V/C) 1.8
6241 G44
Supply Current vs Supply Voltage
TA = 25C TA = -55C
TA = 125C
0 -0.6
0
2
8 6 10 4 TOTAL SUPPLY VOLTAGE (V)
12
6241 G04
Input Bias Current vs Common Mode Voltage
1000 VS = 5V, 0V TA = 125C 700 600 500 400 300 200 100 0 -100 -200 TA = 25C 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 COMMON MODE VOLTAGE (V)
6241 G06
Input Bias Current vs Common Mode Voltage
VS = 5V, 0V
VS = 5V, 0V
TA = 25C
TA = 125C
10 TA = 85C 1
TA = 85C
-300 -400 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 COMMON MODE VOLTAGE (V)
6241 G07
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LTC6240/LTC6241/LTC6242 TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs Temperature
1000 OUTPUT LOW SATURATION VOLTAGE (V) VCM = VS/2 10
TA = 25C 1 TA = 125C 0.1 TA = -55C
OUTPUT HIGH SATURATION VOLTAGE (V)
INPUT BIAS CURRENT (pA)
100 VS = 10V 10 VS = 5V
1
0.1 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (C)
6241 G08
Gain Bandwidth and Phase Margin vs Temperature
VS = 5V
GAIN BANDWIDTH (MHz) 70 CL = 5pF RL = 1k 60 50 PHASE MARGIN PHASE MARGIN (DEG) 80 70 60 50 GAIN (dB) 40 30 20 10 0 -10 5 25 45 65 85 105 125 TEMPERATURE (C)
6241 G12
GAIN BANDWIDTH (MHz)
VS = 1.5V
40 30 20 10
VS = 5V VS = 1.5V
GAIN BANDWIDTH
0 -55 -35 -15
Slew Rate vs Temperature
20 AV = -2 18 RF = 1k, RG = 500 CONDITIONS: SEE NOTE 12 OUTPUT IMPEDANCE () 16 SLEW RATE (V/s) 14 12 10 8 6 4 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
6241 G15
1k 100 10 1 0.10 0.01 10k AV = 10 AV = 2
COMMON MODE REJECTION (dB)
VS = 5V FALLING VS = 2.5V FALLING VS = 5V RISING VS = 2.5V RISING
UW
Output Saturation Voltage vs Load Current (Output Low)
VS = 5V, 0V 10
Output Saturation Voltage vs Load Current (Output High)
VS = 5V, 0V TA = 25C 1 TA = 125C TA = -55C 0.1
0.01
0.001 0.1
10 1 LOAD CURRENT (mA)
100
6241 G09
0.01 0.1
10 1 LOAD CURRENT (mA)
100
6241 G10
Open Loop Gain vs Frequency
PHASE 120 CL = 5pF 100 RL = 1k VCM = VS/2 80 60 GAIN
Gain Bandwidth and Phase Margin vs Supply Voltage
TA = 25C CL = 5pF RL = 1k PHASE MARGIN 70 60 PHASE MARGIN (DEG) 50 40 30 20 10 0 0 2 4 6 8 10 TOTAL SUPPLY VOLTAGE (V) 12
6241 G14
40 30
VS = 5V VS = 1.5V VS = 5V VS = 1.5V
PHASE (DEG)
40 20 0
-20 -40 -60
GAIN BANDWIDTH
-20 10k
100k
1M 10M FREQUENCY (Hz)
-80 100M
6241 G13
Output Impedance vs Frequency
10k TA = 25C VS = 2.5V 100 90 80 70 60 50 40 30 20 10 0 100k 1M FREQUENCY (Hz) 10M
6241 G16
Common Mode Rejection Ratio vs Frequency
TA = 25C VS = 2.5V
AV = 1
-10 10k
100k
1M 10M FREQUENCY (Hz)
100M
6241 G17
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13
LTC6240/LTC6241/LTC6242 TYPICAL PERFOR A CE CHARACTERISTICS
Channel Separation vs Frequency
0 -10 -20 -30 VOLTAGE GAIN (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 10k 100k 1M 10M FREQUENCY (Hz) 100M
6241 G18
POWER SUPPLY REJECTION RATIO (dB)
INPUT CAPACITANCE (pF)
Minimum Supply Voltage
100 80 CHANGE IN OFFSET VOLTAGE (V) 60 40 20 0 -20 -40 -60 -80 -100 0 1 2345678 TOTAL SUPPLY VOLTAGE (V) 9 10 TA = 125C TA = -55C TA = 25C OUTPUT SHORT-CIRCUIT CURRENT (mA) VCM = VS/2 50 40 30 20 10 0 -10 -20 -30 -40
INPUT VOLTAGE (V)
Open Loop Gain
120 100 INPUT VOLTAGE (V) 80 60 40 20 0 -20 0 1 2 3 4 OUTPUT VOLTAGE (V) 5
6241 G24
TA = 25C VS = 5V, 0V
OFFSET VOLTAGE (V)
INPUT VOLTAGE (V)
RL = 10k RL = 1k
14
UW
TA = 25C VS = 2.5V AV = 1
6241 G21
Power Supply Rejection Ratio vs Frequency
90 80 70 60 50 POSITIVE SUPPLY 40 30 20 10 0 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M
6241 G19
Input Capacitance vs Frequency
16 14 12 10 8 6 4 2 0 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M
6241 G20
TA = 25C VS = 2.5V
VS = 1.5V
CCM
NEGATIVE SUPPLY
Output Short Circuit Current vs Power Supply Voltage
120 TA = -55C TA = 125C 100 80 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 POWER SUPPLY VOLTAGE (V) 5.0
Open Loop Gain
TA = 25C VS = 3V, 0V
SINKING
TA = 25C
RL = 100k RL = 10k
TA = 125C SOURCING TA = -55C
-50 1.5
0
0.5
1.0 1.5 2.0 OUTPUT VOLTAGE (V)
2.5
3.0
6241 G23
6241 G22
Open Loop Gain
100 80 60 40 20 0 -20 -40 -60 -5 -4 -3 -2 -1 0 1 2 3 OUTPUT VOLTAGE (V) 4 5 RL = 10k RL = 1k TA = 25C VS = 5V 500 400 300 200 100 0 -100 -200 -300 -400
Offset Voltage vs Output Current
VS = 5V TA = 125C TA = 25C TA = -55C
-500 -50 -40 -30 -20 -10 0 10 20 30 40 50 OUTPUT CURRENT (mA)
6241 G26
6241 G25
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LTC6240/LTC6241/LTC6242 TYPICAL PERFOR A CE CHARACTERISTICS
Warm-Up Drift vs Time
25 CHANGE IN OFFSET VOLTAGE (V) 20 15 10 5 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 TIME AFTER POWER UP (s)
6241 G27
TA = 25C
40 30 20 10 0 1 10 100 1k FREQUENCY (Hz) 10k 100k
VS = 2.5V
VS = 1.5V
VOLTAGE NOISE (200nV/DIV)
NOISE VOLTAGE (nV/Hz)
VS = 5V
Noise Current vs Frequency
1000
1k
NOISE CURRENT (fA/Hz)
100 OVERSHOOT (%) 40 30
- +
1k
RS CL
OUTPUT SERIES RESISTANCE ()
TA = 25C VS = 2.5V VCM = 0V
10
1 10 0.1 100 0 10k 1k FREQUENCY (Hz) 100k
6241 G42
Series Output Resistance and Overshoot vs Capacitive Load
60 50 OVERSHOOT (%) 40 30
75pF
500
- +
1k
RS
SETTLING TIME (s)
CL
1k
SETTLING TIME (s)
RS = 10
20
10 0 10 100 CAPACITIVE LOAD (pF)
UW
RS = 50
VS = 2.5V AV = -2
6241 G30
Noise Voltage vs Frequency
60 50 TA = 25C VS = 2.5V VCM = 0V
0.1Hz to 10Hz Voltage Noise
VS = 5V, 0V
TIME (1s/DIV)
6241 G28 6241 G11
Series Output Resistance and Overshoot vs Capacitive Load
60 50
75pF
Minimum Output Series Resistance vs Capacitive Load
1000
VS = 2.5V <30% OVERSHOOT
100
10
RS = 10
20
RS = 50
1
VS = 2.5V AV = -1 10 100 CAPACITIVE LOAD (pF) 1000
6241 G29
0.1 10pF 100pF 1000pF 0.01F 0.1F CAPACITIVE LOAD
1F
10F
6241 G45
Settling Time vs Output Step (Non-Inverting)
3.5 TA = 25C VS = 5V 3.0 A = 1 V 2.5 2.0 1mV 1.5 1.0 0.5 10mV 0 -4 -3 -2 -1 0 1 2 OUTPUT STEP (V) 3 4
VIN
Settling Time vs Output Step (Inverting)
3.0 TA = 25C VS = 5V 2.5 AV = -1 2.0 1.5 1.0 10mV 0.5 0 -4 -3 -2 -1 0 1 2 OUTPUT STEP (V) 3 4 10mV 1mV
1k
- +
- +
VOUT
VIN
1k VOUT 1k
1mV
1mV 10mV
1000
6241 G31
6241 G32
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15
LTC6240/LTC6241/LTC6242 TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Undistorted Output Signal vs Frequency
10 OUTPUT VOLTAGE SWINGING (VP-P) 9 8 DISTORTION (dBc) 7 6 5 4 3 TA = 25C 2 VS = 5V HD2, HD3 < -40dBc 1 10k 100k 1M FREQUENCY (Hz) -90 -100 10k -90 -100 10k AV = +2 AV = -1 -30
-60 -70
RL = 1k, 2ND
DISTORTION (dBc)
Distortion vs Frequency
-30 VS = 2.5V AV = 2 -40 V OUT = 2VP-P DISTORTION (dBc) DISTORTION (dBc) -50 -60 RL = 1k, 2ND -70 -80 -90 -100 10k -30
RL = 1k, 3RD -90 -100 10k VS = 2.5V AV = 1 RL = 100k 1M FREQUENCY (Hz) 10M
6241 G37 6241 G38
100k 1M FREQUENCY (Hz)
Large Signal Response
0V
VS = 5V AV = 1 RL =
16
UW
6241 G33 6241 G36 6241 G39
Distortion vs Frequency
VS = 2.5V AV = 1 -40 V OUT = 2VP-P -50 -30
Distortion vs Frequency
VS = 5V AV = 1 -40 V OUT = 2VP-P -50 -60 -70 -80 RL = 1k, 2ND RL = 1k, 3RD
RL = 1k, 3RD -80
10M
100k 1M FREQUENCY (Hz)
10M
6241 G34
100k 1M FREQUENCY (Hz)
10M
6241 G35
Distortion vs Frequency
VS = 5V AV = 2 -40 V OUT = 2VP-P -50 -60 -70 RL = 1k, 3RD -80 RL = 1k, 2ND 0V
Small Signal Response
10M
Large Signal Response
Output Overdrive Recovery
0V
0V VIN (1V/DIV) 0V VOUT (2V/DIV) VS = 2.5V AV = -1 RL = 1k
6241 G40
VS = 2.5V AV = 3 RL =
500ns/DIV
6241 G41
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LTC6240/LTC6241/LTC6242 APPLICATIO S I FOR ATIO
Amplifier Characteristics Figure 1 is a simplified schematic of the amplifier, which has a pair of low noise input transistors M1 and M2. A simple folded cascode Q1, Q2 and R1, R2 allow the input stage to swing to the negative rail, while performing level shift to the Differential Drive Generator. Low offset voltage is accomplished by laser trimming the input stage. Capacitor C1 reduces the unity cross frequency and improves the frequency stability without degrading the gain bandwidth of the amplifier. Capacitor Cm sets the overall amplifier gain bandwidth. The differential drive generator supplies signals to transistors M3 and M4 that swing the output from rail-to-rail. The photo of Figure 2 shows the output response to an input overdrive with the amplifier connected as a voltage follower. If the negative going input signal is less than a diode drop below V-, no phase inversion occurs. For input signals greater than a diode drop below V-, limit the current to 3mA with a series resistor RS to avoid phase inversion. ESD The LTC6240/LTC6241/LTC6242 have reverse-biased ESD protection diodes on all input and outputs as shown in Figure 1. If these pins are forced beyond either supply, unlimited current will flow through these diodes. If the current is transient and limited to one hundred milliamps or less, no damage to the device will occur.
V+ ITAIL CM V- DESD1 VIN+ VIN- DESD3 V- V+ DESD4 V+ DESD2 M1 M2 C1 V- BIAS V Q1 Q2 M4 RS VIN V-
6241 F01
DIFFERENTIAL DRIVE GENERATOR
-
R1
R2
Figure 1. Simplified Schematic
U
The amplifier input bias current is the leakage current of these ESD diodes. This leakage is a function of the temperature and common mode voltage of the amplifier, as shown in the Typical Performance Curves. Noise The LTC6240/LTC6241/LTC6242 exhibit exceptionally low 1/f noise in the 0.1Hz to 10Hz region. This 550nVP-P noise allows these op amps to be used in a wide variety of high impedance low frequency applications, where Zero-Drift amplifiers might be inappropriate due to their charge injection. In the frequency region above 1kHz the LTC6240/LTC6241/ LTC6242 also show good noise voltage performance. In this frequency region, noise can easily be dominated by the total source resistance of the particular application. Specifically, these amplifiers exhibit the noise of a 3.1k resistor, meaning it is desirable to keep the source and feedback resistance at or below this value, i.e. RS + RG||RFB 3.1k. Above this total source impedance, the noise voltage is not dominated by the amplifier. Noise current can be estimated from the expression in = 2qIB, where q = 1.6 * 10-19 coulombs. Equating 4kTRf and R2qIBf shows that for source resistors below 50G the amplifier noise is dominated by the source resistance. See the Typical Characteristics curve Noise Current vs Frequency.
VDD = +2.5V M3 V+ DESD5 VO DESD6 VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE VSS = -2.5V +2.5V
W
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+
LTC6240 VOUT
-
-2.5V
6241 F02
Figure 2. Unity Gain Follower Test Circuit
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17
LTC6240/LTC6241/LTC6242 APPLICATIO S I FOR ATIO
Proprietary design techniques are used to obtain simultaneous low 1/f noise and low input capacitance. Low input capacitance is important when the amplifier is used with high value source and feedback resistors. High frequency noise from the amplifier tail current source, ITAIL in Figure 1, couples through the input capacitance and appears across these large source and feedback resistors. As an example, the photodiode amplifier of Figure 15 on the last page of this data sheet shows the noise results from the LTC6241 and the results of a competitive CMOS amplifier. The LTC6241 output is the ideal noise of a 1M resistor at room temperature, 130nVHz.
+2.5
+
1/4 LTC6242
1k
-
-2.5 1k
10
+
1/4 LTC6242
1k
-
VIN 10 VO
1k
+
1/4 LTC6242
1k
-
10
1k
+
1/4 LTC6242
1k
-
10
1k
6241 F03
Figure 3. Parallel Amplifier Lowers Noise by 2x
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18
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Half the Noise The circuit shown in Figure 3 can be used to achieve even lower noise voltage. By paralleling 4 amplifiers the noise voltage can be lowered by 4, or half as much noise. The comes about from an RMS summing of uncorrelated noise sources. This circuit maintains extremely high input resistance, and has a 250 output resistance. For lower output resistance, a buffer amplifier can be added without influencing the noise. Stability The good noise performance of these op amps can be attributed to large input devices in the differential pair. Above several hundred kilohertz, the input capacitance rises and can cause amplifier stability problems if left unchecked. When the feedback around the op amp is resistive (RF), a pole will be created with RF , the source resistance, source capacitance (RS, CS), and the amplifier input capacitance. In low gain configurations and with RF and RS in even the kilohm range (Figure 4), this pole can create excess phase shift and possibly oscillation. A small capacitor CF in parallel with RF eliminates this problem. Low Noise Single-Ended Input to Differential Output Amplifier The circuit on the first page of the data sheet is a low noise single-ended input to differential output amplifier, with a 200k input impedance. The very low input bias current of the LTC6241 allows for these large input and feedback resistors. The 200k resistors, R1 and R2, along with C1 and C2 set the -3dB bandwidth to 80kHz. Capacitor C3 is used to cancel effects of input capacitance, while C4 adds
CF RF
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-
RS CS CIN OUTPUT
+
6241 F04
Figure 4. Compensating Input Capacitance
LTC6240/LTC6241/LTC6242 APPLICATIO S I FOR ATIO
phase lead to compensate the phase lag of the second amplifier. The op amp's good input offset voltage match and low input bias current means that the typical differential output offset voltage is less than 40V. A noise spectrum plot of the differential output is shown in Figure 5.
DIFFERENTIAL OUTPUT VOLTAGE DENSITY (nV/Hz) 140 VS = 2.5V TA = 25C 120 -3dB BW = 80kHz 100 80 60 40 20 0 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz)
6241 F05
Figure 5. Differential Output Noise
Achieving Low Input Bias Current The DD package is leadless and makes contact to the PCB beneath the package. Solder flux used during the attachment of the part to the PCB can create leakage current paths and can degrade the input bias current performance of the part. All inputs are susceptible because the backside paddle is connected to V- internally. As the input voltage changes or if V- changes, a leakage path can be formed and alter the observed input bias current. For lowest bias current, use the LTC6240/LTC6241 in the SO-8 and provide a guard ring around the inputs that are tied to a potential near the input voltage. Layout Considerations and a PCB Guard Ring In high source impedance applications such as pH probes, photodiodes, strain gauges, et cetera, the low input bias current of these parts requires a clean board layout to minimize additional leakage current into a high impedance signal node. A mere 100G of PC board resistance between a 5V supply trace and an input trace adds 50pA of leakage current, far greater then the input bias current of the operational amplifier. A guard ring around the high-impedance input traces driven by a low-impedance
R
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source equal to the input voltage prevents such leakage problems. The guard ring should extend as far as necessary to shield the high impedance signal from any and all leakage paths. Figure 6 shows the use of a guard ring on the LTC6241 in a unity gain configuration. In this case the guard ring is connected to the output and is shielding the high impedance non-inverting input from V-. Figure 7 shows the inverting gain configuration. A Digitally Programmable AC Difference Amplifier The LTC6241 configured as a difference amplifier, can be combined with a programmable gain amplifier (PGA) to obtain a low noise high speed programmable difference amplifier. Figure 8 shows the LTC6241 based as a single-supply AC amplifier. One LTC6241 op amp is used at the circuit's input as a standard four resistor difference
LTC6241 S8 OUT+ NO SOLDER MASK OVER THE GUARD RING R IN+ LEAKAGE CURRENT GUARD RING V-
LTC6241 F06
W
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NO LEAKAGE CURRENT
IN-
Figure 6. Sample Layout. Unity Gain Configuration, Using Guard Ring to Shield High Impedance Input from Board Leakage
LTC6241 S8 OUT+ R
IN- VIN IN+
GND V-
LTC6241 F07
Figure 7. Sample Layout. Inverting Gain Configuration, Using Guard Ring to Shield High Impedance Input from Board Leakage
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19
LTC6240/LTC6241/LTC6242 APPLICATIO S I FOR ATIO
R3 C1 V+ 0.1F 8 7 6 5 LTC6910-2 G2 G1 G0 R1 V1
+
1/2 LTC6241
OUT AGND IN V- 1 2 3 4 VOUT
-
R2 V2 C2 R1 = R2 = R3 = R4 0.1F V+ R4 100 C3
1000pF R6 20k
1/2 LTC6241
1 2 LT6650 5 1F 3 4 1F 1k V+ VREF
DIGITAL INPUTS G2 G1 GO 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
GAIN 0 -1 -2 -4 -8 -16 -32 -64
VOUT = (V1 - V2) GAIN + VREF
R5 VREF = 0.4 * +1 R6
R5 = 10k * ( 5 * VREF - 2) R6 = 20k
-3d BANDWIDTH = ( fHIGH - fLOW ) fHIGH = 1 GAIN = f 2 * * R3 * C1 LOW 2 * * R7 * C3
6241 F08
Figure 8. Wideband Difference Amplifier with High Input Impedance and Digitally Programmable Gain
amplifier. The low bias current and current noise of the LTC6241 allow the use of high valued input resistors, 100k or greater. Resistors R1, R2, R3 and R4 are equal and the gain of the difference amplifier is one. An LTC6910-2 PGA amplifies the difference amplifier output with inverting gains of -1, -2, -4, -8, -16, -32 and -64. The second LTC6241 op amp is used as an integrator to set the DC output voltage equal to the LT6650 reference voltage VREF. The integrator drives the PGA analog ground to provide a feedback loop, in addition to blocking any DC voltage through the PGA. The reference voltage of the LT6650 can be set to a voltage from 400mV to V+ - 350mV with resistors R5 and R6. If R6 is 20k or less, the error due to the LT6650 op amp bias current is negligible. The low voltage offset and drift of the LTC6241 integrator will not
20
-
R5
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R7
+
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contribute any significant error to the LT6650 reference voltage. The LT6650 VREF voltage has a maximum error of 2% with 1% resistors. The upper -3dB frequency of the amplifier is set by resistor R3 and capacitor C1 and is limited by the bandwidth of the PGA when operated at a gain of 64. Capacitor C2 is equal to C1 and is added to maintain good common mode rejection at high frequency. The lower -3dB frequency is set by the integrator resistor R7, capacitor C3, and the gain setting of the LTC6910-2 PGA. This lower -3dB zero frequency is multiplied by the PGA gain. The rail-to-rail output of the LTC6910-2 PGA allows for a maximum output peak-to-peak voltage equal to twice the VREF voltage. At the maximum gain setting of 64, the maximum peak-to-peak difference between inputs V1 and V2 is equal to twice VREF divided by 64. Example Design: Design a programmable gain AC difference amplifier, with a bandwidth of at least 10Hz to 100kHz, an input impedance equal to or greater than 100k, and an output DC reference equal to 1V. a. Select input resistors R1, R2, R3 and R4 equal to 100k. b. If the upper -3dB frequency is 100kHz then C1 = 1/(2 * R2 * f3dB) = 1/(6.28 * 100k * 100kHz) = 15pF (to the nearest 5% value) and C2 = C1 = 15pF. c. Select R7 equal to one 1M and set the lower -3dB frequency to 10Hz at the highest PGA gain of 64, then C3 = Gain/(2 * R7 * f3dB) = 64/(6.28 * 100k * 10Hz) = 1uF. Lower gains settings will give a lower f3dB. d. Calculate the value of R5 to set the LT6650 reference equal to 1V; VREF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF - 1). For R6 = 20k, R5 = 30k With VREF = 1V the maximum input difference voltage is equal to 2V/64 = 31.2mV. 40nVpp Noise, 0.05V/C Drift, Chopped FET Amplifier Figure 9's circuit combines the 5V rail-to-rail performance of the LTC6241HV with a pair of extremely low noise JFETs configured in a chopper based carrier modulation scheme
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LTC6240/LTC6241/LTC6242 APPLICATIO S I FOR ATIO
to achieve an extraordinarily low noise and low DC drift. The performance of this circuit is suited for the demanding transducer signal conditioning situations such as high resolution scales and magnetic search coils. The LTC1799's output is divided down to form a 2-phase 925Hz square wave clock. This frequency, harmonically unrelated to 60Hz, provides excellent immunity to harmonic beating or mixing effects which could cause instabilities. S1 and S2 receive complementary drive, causing A1 to see a chopped version of the input voltage. A1's square wave output is synchronously demodulated by S3 and S4. Because these switches are synchronously driven
5V 1F 1F TO LTC201 V + PIN
+
5V 18.5kHz 74C90 / 10
5V 74C74 / 2 Q 925Hz Q
V+ 5V DIV LTC1799 OUT RSET 54.2k* 5V O1 8 898** 30.1 INPUT 0.01F 10 9 O2 499** -5V 7 S1 S2 11 LSK389 6 898**
TO O1 POINTS
TO O2 POINTS
O2 1 1F 3 S3 S4 15 16 10k 1F O1 14 240k
- +
A1 LTC6241HV 10M
1F 2
* = 0.1% METAL FILM RESISTOR ** = 1% METAL FILM RESISTOR = LTC201 QUAD = LSK389 = LINEAR INTEGRATED SYSTEMS FREMONT, CA
NOISE = 40nVP-P 0.1Hz TO 10Hz OFFSET = 1V DRIFT = 0.05V/C R2 +1 GAIN = 10 OPEN-LOOP GAIN = 10 9 I BIAS = 500pA
Figure 9. Ultra Low Noise Chopper Amplifier
+
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with the input chopper, proper amplitude and polarity information is presented to A2, the DC output amplifier. This stage integrates the square wave into a DC voltage, providing the output. The output is divided down (R2 and R1) and fed back to the input chopper where it serves as a zero signal reference. Gain, in this case 1000, is set by the R1-R2 ratio. Because A1 is AC coupled, its DC offset and drift do not affect the overall circuit offset, resulting in the extremely low offset and drift noted. The JFETs have an input RC damper that minimizes offset voltage contribution due to parasitic switch behavior, resulting in the 1V offset specification.
-5V TO LTC201 V - PIN
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-
A2 LTC6241HV OUTPUT
+
R2 10k
R1 10
6241 F09
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LTC6240/LTC6241/LTC6242 APPLICATIO S I FOR ATIO
The noise measured over a 50 second interval, in Figure 10, is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is attributed to the input JFET's die size and current density.
VERT = 20nV/DIV
HORIZ = 5s/DIV
Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth
Low Noise Shock Sensor Amplifiers Figures 11 and 12 show the amplifiers realizing two different approaches to amplifying signals from a capacitive sensor. The sensor in both cases is a 770pF piezoelectric shock sensor accelerometer, which generates charge under physical acceleration. Figure 11 shows the classical "charge amplifier" approach. The LTC6240 is in the inverting configuration so the sensor looks into a virtual ground. All of the charge generated
+
SHOCK SENSOR MURATA-ERIE PKGS-00LD 770pF LTC6240
-
Cf 7.7pF
VOUT = 110mV/g
CABLE HAS UNKNOWN C
Rf 1G BIAS RESISTOR VISHAY-TECHNO CRHV2512AF1007G (OR EQUIVALENT)
MAIN GAIN-SETTING ELEMENT IS A CAPACITOR
Figure 11. Classical Inverting Charge Amplifier
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by the sensor is forced across the feedback capacitor by the op amp action. Because the feedback capacitor is 100 times smaller than the sensor, it will be forced to 100 times what would have been the sensor's open circuit voltage. So the circuit gain is 100. The benefit of this approach is that the signal gain of the circuit is independent of any cable capacitance introduced between the sensor and the amplifier. Hence this circuit is favored for remote accelerometers where the cable length may vary. Difficulties with the circuit are inaccuracy of the gain setting with the small capacitor, and low frequency cutoff due to the bias resistor working into the small feedback capacitor. Figure 12 shows a non-inverting amplifier approach. This approach has many advantages. First of all, the gain is set accurately with resistors rather than with a small capacitor. Second, the low frequency cutoff is dictated by the bias resistor working into the large 770pF sensor, rather than into a small feedback capacitor, for lower frequency response. Third, the non-inverting topology can be paralleled and summed (as shown) for scalable reductions in voltage noise. The only drawback to this circuit is that the parasitic capacitance at the input reduces the gain slightly. This circuit is favored in cases where parasitic input capacitances such as traces and cables will be relatively small and invariant.
VS+
6241 F10
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SHOCK SENSOR MURATA-ERIE PKGS-00LD 770pF 100 1G BIAS RESISTOR VISHAY-TECHNO CRHV2512AF1007G (OR EQUIVALENT) 100
6241 F11
1/2 LTC6241HV
-
10k
1k VOUT 1k
+
1/2 LTC6241HV
-
VS- 10k
6241 F12
VOUT = 110mV/g VS = 1.4V to 5.5V BW = 0.2Hz to 10kHz
Figure 12. Low Noise Non-Inverting Shock Sensor Amplifier
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LTC6240/LTC6241/LTC6242 APPLICATIO S I FOR ATIO
1M Transimpedance Amplifier with 43nV/Hz Output Noise In a normal 1M transimpedance amplifier, like that shown on the back page of this data sheet, the output noise density must be at least 130nV/Hz at room temperature. This is true even should the op amp be perfectly noiseless, because the 1M resistor provides 130nV/Hz of voltage noise at room temperature independently of the op amp. The circuit of Figure 13 provides an overall transimpedance gain of 1M, but it has an output noise density of only 43nV/Hz, about 1/3 of the normal transimpedance amplifier. It does this by taking a higher initial transimpedance gain of 10M and then attenuating by a factor of 10. The transistor section provides voltage gain and works on a 54V supply voltage to guarantee adequate output swing.
5V
+
3pF PHOTODIODE -1.5V LTC6240HV MPSA06 10k -5V 1k 100pF -5V 10k 2.4k 43k
-
Figure 13. 1M Transimpedance Amplifier with 43nV/Hz Output Noise
LT1019-2.5
180nV/Hz
Figure 14. Low Noise Reference Buffer
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By achieving an output swing of 50V before attenuation, the circuit provides an output swing to 5V after attenuation. The 10M resistor sets the gain of the TIA stage and has a noise density of 400nV/Hz. After attenuation, the effective TIA gain drops to 1M while the noise floor drops to 40nV/Hz, which clearly dominates the observed 43nV/Hz. Note the additional benefit that the offset voltage of the op amp is divided by 10. Worst case output offset for this circuit is 150V over temperature. Reference Buffer Figure 14 shows the LTC6240 being utilized as a buffer in conjunction with the LT1019 reference. The passive R-C filter attenuates the reference noise and the LTC6240 provides a low noise buffer, resulting in an output noise of 8nV/Hz.
54V 0.3pF 33k MPSA06 10M 1% 10M GAIN (10V/A) 9.09k 1% 1/4W VOUT 1M GAIN (1V/A) 1k 1%
6241 F13
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5V 1M 1F
+
LTC6240HV 8nV/Hz
0.2 VOUT 10F CERAMIC OR FILM
6241 F14
-
-5V
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LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTIO U
DHC Package 16-Lead Plastic DFN (5mm x 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05 3.50 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 4.40 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 0.10 (2 SIDES) R = 0.20 TYP R = 0.115 TYP 9 16 0.40 0.10 3.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 8 0.200 REF 0.75 0.05 4.40 0.10 (2 SIDES) 1 0.25 0.05 0.50 BSC 1.65 0.10 (2 SIDES) PIN 1 NOTCH
(DHC16) DFN 1103
1.65 0.05 2.20 0.05 (2 SIDES)
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.254 MIN
.150 - .165
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE
.0532 - .0688 (1.35 - 1.75)
.004 - .0098 (0.102 - 0.249)
.009 (0.229) REF
0 - 8 TYP
.229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988)
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0204
1
23
4
56
7
8
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LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTIO U
DD Package 8-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 TYP 5 0.675 0.05 0.38 0.10 8 3.00 0.10 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK (NOTE 6)
(DD8) DFN 1203
3.5 0.05 1.65 0.05 2.15 0.05 (2 SIDES)
1.65 0.10 (2 SIDES)
0.200 REF
0.75 0.05
4 0.25 0.05 2.38 0.10 (2 SIDES)
1 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE
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LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTIO U
S5 Package 5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62 MAX 0.95 REF 2.90 BSC (NOTE 4) 1.22 REF 1.4 MIN 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 - 0.45 TYP 5 PLCS (NOTE 3) 0.95 BSC 0.80 - 0.90 0.20 BSC 1.00 MAX DATUM `A' 0.01 - 0.10 1.90 BSC
S5 TSOT-23 0302 REV B
3.85 MAX 2.62 REF
0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
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LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTIO U
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.045 .005 .050 BSC
8 .189 - .197 (4.801 - 5.004) NOTE 3 7 6 5 .160 .005 .228 - .244 (5.791 - 6.197) .150 - .157 (3.810 - 3.988) NOTE 3 1 2 3 4 .053 - .069 (1.346 - 1.752) 0- 8 TYP .004 - .010 (0.101 - 0.254) .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC
SO8 0303
.245 MIN
.030 .005 TYP RECOMMENDED SOLDER PAD LAYOUT
.010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254)
.016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC6240/LTC6241/LTC6242 TYPICAL APPLICATIO U
1M TIA 150kHz 3RD ORDER BUTTERWORTH FILTER
+
1/2 LTC6241
R1 866 C1 1500pF
R2 1.69k
R3 2k C3 180pF
C2 1500pF
+1.5V
+
1/2 LTC6241
-
SFH213FA OR EQUIVALENT (4pF) -1.5V
RF 1M
-
-1.5V
6241 TA02a
CF 1pF
Figure 15. Ultralow Noise 1M 150kHz Photodiode Amplifier
LTC6241 Output Noise Spectrum. 1M Resistor Noise Dominates; Ideal Performance
Competition Output Noise Spectrum. Op Amp Noise Dominates; Performance Compromised
30nV/Hz PER DIV
0V 1kHz 10kHz/DIV 101kHz
6241 TA02b
0V 1kHz 10kHz/DIV 101kHz
6241 TA02c
RELATED PARTS
PART NUMBER LTC1151 LT1792 LTC2050 LTC2051/LTC2052 LTC2054/LTC2055 LTC6244 DESCRIPTION 15V Zero-Drift Op Amp Low Noise Precision JFET Op Amp Zero-Drift Op Amp Dual/Quad Zero-Drift Op Amp Single/Dual Zero-Drift Op Amp Dual 50MHz Rail-to-Rail Op Amp COMMENTS Dual High Voltage Operation 18V 6nV/Hz Noise, 15V Operation 2.7 Volt Operation, SOT-23 Dual/Quad Version of LTC2050 in MS8/GN16 Packages Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages 100V VOS(MAX), 1pA IBIAS, 40V/V, Slew Rate
30nV/Hz PER DIV
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28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0107 REV C * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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